In advanced semiconductor integrated circuits (ICs), a MOSFET is widely used to achieve various objects and electronic applications. For example, the cell of dynamic random access memory (DRAM) is mostly composed of a MOSFET and a capacitor nowadays. Along with the development of the semiconductor technology, the size of a MOSFET is greatly reduced to submicron range in order to increase the integration of the semiconductor memory. In other words, more memory cells composed of the MOSFET can be incorporated on a single semiconductor substrate. The increase of the integration brings two advantages: rising of the production rate and falling of the production cost.
However, in the submicron MOSFET, there are several technical problems to be solved. One of these problems is the so-called hot carrier effect which will be described in the following. As a result of the size reduction, the carrier channel between the source and the drain regions in the MOSFET is shortened. Therefore, carriers with extremely high energy are generated in the channel when carriers supplied from the source/drain region are sharply accelerated by a high electric field near a pinch-off region in vicinity of the source/drain junction. These carriers are named as hot carriers due to the extremely high energy. The hot carriers may inject into the gate oxide and deteriorate the MOSFET.
As a solution to the hot carrier problem, a MOSFET with a lightly doped drain (LDD) structure is proposed. In the following, the process for fabricating the LDD MOSFET will be described in detail with reference to FIGS. 1(a) to 1(f).
FIGS. 1(a) to 1(f) are cross-sectional views showing the conventional process for fabricating an LDD MOSFET, especially an N-type LDD MOSFET (referred to as NMOS in the following) . As shown in FIG. 1(a), a gate oxide film 12 is formed on a semiconductor substrate 10 such as silicon. Next, a polysilicon film 13 and a cap gate oxide film 14 are formed on the gate oxide film 12, respectively.
Referring to FIG. 1(b), the cap gate oxide film 14 and the polysilicon film 13 are etched through applying a selective etching method so as to define a gate electrode 13a covered with an oxide film 14a on the gate oxide film 12.
Referring to FIG. 1(c), a first ion implantation 110 using phosphorus ions is conducted over the whole surface of the resulting structure shown in FIG. 1(b ) with a light dose and a low implanting energy to form lightly doped N-type source/drain regions 101.
Referring to FIG. 1(d), a silicon oxide film 15 is deposited over the whole surface of the resulting structure shown in FIG. 1(c) through the conventional chemical vapor deposition (CVD) method. Subsequently, the silicon oxide film 15 and the gate oxide film 12 are partially etched through the conventional reactive ion etching (RIE) method such that part of the silicon oxide film 15 and the gate oxide film 12 are remained to form sidewall spacers 15a adjacent to each of opposite sides of the gate electrode 13a and the oxide film 14a, as shown in FIG. 1(e).
Thereafter, referring to FIG. 1(f), using the sidewall spacers 15a as a mask, a second ion implantation 120 using arsenic ions is conducted over the whole surface of the resulting structure shown in FIG. 1(e) with a larger dose and a higher implanting energy than the first ion implantation. As a result, heavily doped N-type source/drain regions 102 having deeper junctions are formed and the conventional LDD NMOS is completed.
It is apparent in FIG. 1(f) that LDD NMOS has a self-aligned lightly doped N-type region 101a formed between the channel 103 and the heavily doped N-type source/drain region 102. Because this lightly doped N-type region 101a spreads out the high electric field in vicinity of the drain junction, the above-mentioned carrier electrons supplied from the source region are prevented from extraordinary high field's acceleration. Consequently, the hot carrier problem generally suffered in submicron MOSFET is avoided through the use of the LDD structure.
Although the effectiveness and achievement of the LDD structure is evidential, however, the conventional process still has several disadvantages.
In the first place, the lightly doped N-type region 101a is formed before the formation of the sidewall spacer 15a, so it is subjected to the thermal budget associated with the formation of the sidewall spacer 15a. In other words, the lightly doped N-type region 101a extends in both vertical and horizontal direction during the formation of the sidewall spacer as a result of the transient enhanced diffusion (TED) of the LDD dopant (i.e., phosphorus ions in LDD NMOS case).
Further, the first ion implantation 110 for forming the lightly doped N-type region 101a produces defects, such as silicon interstitials, in the semiconductor substrate. These defects will interact with the dopant, resulting in TED of the dopant.
At last, heavily doped N-type source/drain region 102 formed through the second ion implantation after the formation of the sidewall spacer 15a generates much more defects and further enhances TED of the dopant.
Therefore, it is difficult for the conventional process to achieve an ultra-shallow junction applicable to submicron device.